In a multi-channel network system, in order to clear the fault of a certain channel or to charge data streams in the network system, it is necessary to sort data packets and to calculate, on that basis, the number of each type of data packets transmitted and received in the channel of the network system respectively.
In the conventional art, generally two methods are adopted to calculate the number of data packets in the network system. The first method is to implement by adopting a register, for example, supposing a network system has n channels, each channel has m types of data packets and each type of data packets needs a k-bit counter, since one k-bit register can realize one k-bit binary counter, then it is necessary to occupy at least n*m*k registers to realize the counting of the data packets; moreover, each counter needs to have a reset function; since each counter having the reset function needs a Look-Up-Table (LUT), then n*m*k LUTs are needed, wherein both the register and the LUT belong to logical resources and are used for performing logical operation. The second method is to implement by adopting a Random Access Memory (RAM); when a certain type of data packets arrives at a monitor system of the data packets, and count pulses of the data packets are generated, the monitor system reads out the value of the counter from an address corresponding to the RAM, and adds 1 to the value and then writes the value to the RAM. The first implementation method has an advantage of rapid counting speed, but has a disadvantage of occupying a lot of logical resources when counting a plurality of channels and a plurality of data packets for relatively more counters and LUTs are used. The second implementation method has an advantage of occupying relatively less register resources, but has a disadvantage that the operation speed of the counter cannot meet requirements of the high-speed technology if the count pulses are dense for 3 clock periods are needed to read and write in the RAM.
In the patent application entitled “Method of multi-port received and transmitted packets number statistic in network information exchange” of which the application number is 03132077.5, a method for counting data packets is disclosed, which comprises: using a Field-Programmable Gate Array (FPGA) to make packet buffering and classified counting in a bus switching course; arranging an RAM in the FPGA; especially adopting the RAM in the FPGA to store the classified counting result. This method uses RAM resources to replace trigger resources so as to store the count value of a counter, thus solving the problem of counting overmany triggers consumed and reducing the cost. However, this method has two defects. The first detect is that only RAM is adopted to implement counting; the reading and rewriting of the data in the RAM needs at least 3 clock periods, however, the application scene of this patent requires to be in 96 clock periods, thus the number of data packets needed to be counted cannot exceed 32; otherwise, there is not enough time to process; therefore, this method has great limitations. The second defect is that although this method can count the data packets of a plurality of channels simultaneously, it cannot reset the counter of a single channel, thus if a certain channel needs to restart counting, the entire system has to be reset; therefore, the flexibility of the system is reduced.